Many technological advances in the computer industry have depended upon the ability of semiconductor memory devices to store and retrieve ever increasing amounts of data quickly and inexpensively. Thus, the development of the semiconductor memory has played a major role in the advancement of the computer industry over the past few decades.
Most modern computer systems utilize a Random Access Memory (RAM), which emphasizes the ability to examine each stored piece of data independently of any other piece of data. However, with the drive for computer systems to become increasingly faster, there has become a need for memory devices to execute faster searches.
The Content Addressable Memory (CAM) is a relatively new memory device that accelerates applications requiring fast searches, such as database lists. CAMs provide the ability to compare a desired piece of information against an entire list of pre-stored entries simultaneously. This function enables a decrease in search time by an order of magnitude.
CAMs utilize several types of instructions in order to carry out these rapid comparisons. For example, one instruction may activate a small fraction of the total number of bit lines (e.g., 8 or 16) present in the CAM. Such an instruction may be useful where the CAM has been partitioned and only one section of the total storage area needs to be searched for a particular compare operation. Another instruction may activate all of the bit lines (e.g., 84 or more depending upon the memory array architecture) where all storage areas of the CAM require reading.
Instructions that activate only a small fraction of the total number of bit lines in a CAM typically have a more restrictive speed requirement than instructions that activate all of the bit lines. That is, such instructions typically must be executed faster than those in which all of the CAM's bit lines are activated. To accommodate this speed requirement, a strong bit lines driver (i.e., one capable of driving the bit line to its operating voltage relatively quickly) is required. However, if the same strong bit line driver is used to activate all of the bit lines (e,g., where the second type of instruction is executed), the power and ground currents create spikes that are unacceptable. Accordingly, what is required is a circuit and methods for instruction controllable bit line drivers. SUMMARY OF THE INVENTION
In one embodiment, the present invention provides a method of controlling the slew rate of a bit line driver. Upon receipt of a first signal to activate a first set of bit lines a first set of complementary-pair transistor driver units is energized such that a first set of bit lines is activated within a time period permitted by the first instruction. Upon receipt of a second signal to activate a second set of bit lines, a second set of complementary-pair transistor driver units is energized such that a second set of bit lines is activated within a time period permitted by the second instruction.
In another embodiment, the present invention provides a bit line driver having first driver means for driving a bit line when the bit line driver is in a first state, and second driver means for driving the bit line when the bit line driver is in a second state. The first driver means is configured to produce a first slew rate for the bit line and the second driver means is configured to produce a second slew rate for the bit line. The first and second driver means may include a first and second pair of driver transistors which are each coupled to the bit line. The states of the bit line driver circuit may be defined by instruction signals applied to the driver, and decoder logic may be used to interface the instruction signals to the first and second pair of driver transistors.